This invention relates to a folding stage for a folding analog-to-digital converter, the folding stage comprising:
an input terminal for receiving an input voltage to be folded; PA1 reference means having a plurality of consecutive reference terminals for providing ascending different reference voltages; PA1 a first summing node and a second summing node; PA1 a plurality of differentially coupled transistor pairs, each one of the transistor pairs comprising a current source, a first transistor having a first main electrode coupled to the current source and a control electrode coupled to the input terminal and a second transistor having a first main electrode coupled to the current source and a control electrode coupled to a respective one of the consecutive reference terminals, the second main electrode of the first transistor of consecutive transistor pairs being coupled alternately to the first summing node and to the second summing node, and the second main electrode of the associated second transistor being coupled alternately to the second summing node and to the first summing node; and PA1 a first output node; and PA1 current-to-voltage converter means comprising a first resistor coupled to the first output node to provide a first output voltage and having an input coupled the first summing node. PA1 the first resistor is connected between the first summing node and the first output node; and PA1 the current-to-voltage converter means comprises a transconductance stage having an inverting input coupled to the first summing node and an output coupled to the first output node. PA1 the folding stage further comprises a second output node; PA1 the current-to-voltage converter means further comprises a second resistor connected between the second output node and the second summing node to provide a second output voltage; and PA1 the transconductance stage has a non-inverting input coupled to the second summing node and an inverting output coupled to the second output node, and preferably the folding stage further comprises a second bias current source coupled to the second output node for providing a second bias current to the second summing node via the second resistor. PA1 an input terminal for receiving an input voltage to be converted; PA1 reference means having a plurality of consecutive reference terminals for providing ascending different reference voltages; PA1 a plurality of folding stages, each folding stage comprising: PA1 a first summing node and a second summing node; PA1 a plurality of differentially coupled transistor pairs, each one of the pairs comprising a current source, a first transistor having a first main electrode coupled to the current source and a control electrode coupled to the input terminal and a second transistor having a first main electrode coupled to the current source and a control electrode coupled to a respective one of the consecutive reference terminals, the second main electrode of the first transistor of consecutive transistor pairs being coupled alternately to the first summing node and the second summing node, and the second main electrode of the associated second transistor being coupled alternately to the second summing node and the first summing node; PA1 a first output node; PA1 current-to-voltage converter means comprising a first resistor connected between the first summing node and the first output node to provide a first output voltage and having an input coupled the first summing node and a transconductance stage having an inverting input coupled to the first summing node and an output coupled to the first output node; PA1 a first interpolation network comprising a string of impedance elements interconnected in main string nodes, the main string nodes being connected to respective first output nodes of the folding stages, each one of the impedance elements being comprised of a substring of impedance elements interconnected in substring nodes for providing interpolated versions of voltages at the first output nodes.
The invention also relates to an analog-to-digital (A/D) converter comprising a plurality of such folding stages. Such a folding stage is known from U.S. Pat. No. 4,386,339.
Important considerations in designing an A/D converter are speed, component count and resolution. Full flash converters have a relatively simple architecture. To convert an analog input voltage into an N-bit digital output code, a full flash converter normally employs 2.sup.N -1 input comparators for comparing the input voltage with 2.sup.N -1 corresponding reference voltages. The principal disadvantage of the full flash converter is the high component count due to the large number of input comparators. Several schemes have been proposed to reduce the number of components.
The folding technique is one of the schemes for reducing component count. Folding architectures have been successfully implemented in very high speed bipolar A/D converters. See R. van de Grift et al., "An 8-bit Video ADC Incorporating Folding and Interpolating Techniques", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, December 1987, pp 944-953. Also see R. van de Plassche et al., "An 8-bit 100-MHz Full-Nyquist Analog-to Digital Converter", IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, December 1988, pp 1334-1344. The basic principles of the folding architecture are extensively explained in these references. A folding A/D converter comprises a number of folding stages, each comprising a set of differential pairs responding to the input voltage and a corresponding set of reference voltages. The outputs of the differential pairs are combined in such a way as to generate one or more single ended folding signals or pairs of complementary folding signals having a repetitive rounded triangular or sine wave shape as a function of the input voltage. The folding signals of the folding stages are supplied to respective one's of a group of sample latches for converting the folding signals to a group of least significant bits of the digital output code. The most significant bits are supplied by a group of coarse comparators which operate on the input voltage along a separate channel. In this way the number of latches can be reduced considerably. The number of latches is reduced by the number of times the input signal is folded by the folding stages. However, each latch requires its own folding signal and each folding stage requires as many differential pairs as the number of times the signal has been folded. The more efficient use of the latches is therefore offset by an increasing number of differential pairs in the folding stages. As also known from the afore-mentioned IEEE-references, the number of folding stages can be reduced by interpolating between the folding signals of the folding stages to generate additional folding signals without the need for more folding stages. In this way the interpolation reduces the number of folding stages by the interpolation factor. A combined folding and interpolating architecture results in a compact low-power AID converter.
A problem axises when the folding stage known from U.S. Pat. No. 4,386,339 is to be used in an interpolating and folding A/D converter architecture. In this known folding stage the collectors of consecutive differential transistor pairs are cross coupled and connected to two summing nodes. The current through each summing node is converted to an output voltage by a current-to-voltage converter consisting of a bipolar summing transistor having its base connected to a fixed bias voltage, its emitter connected to the summing node to form a low-impedance current input and its collector connected to a supply voltage via a load resistor to provide the output voltage. For interpolation a string of impedance elements, preferably resistors, is to be connected between the collectors of two consecutive folding stages. Since the interpolation reduces the amplitude of the interpolated signals, the output voltage at the collectors of the summing transistors should be sufficiently high and therefore the resistance value of the load resistor should be sufficiently high as well. The total resistance of the string of interpolation resistors should be large with respect to the load resistors to avoid heavy shunting of the load resistors. High resistance values are undesirable as they require much considerable area in an integrated circuit and reduce the maximum speed as a consequence of the increased sensitivity to parasitic capacitances.